1. Field of the Invention
This invention relates to a bus connection circuit and bus connection system utilizing data pre-fetch functions in a computer system requiring high-speed and large-volume data transfer, and in particular relates to a bus connection circuit and bus connection system utilizing data pre-fetch functions to raise the efficiency of transfer of large volumes of data, in a computer system having an internal PCI bus.
2. Description of the Related Art
In recent years computer systems have widely adopted PCI (Peripheral Component Interconnect) buses as a standard bus specification capable of high-speed transfer of large amounts of data. PCI is a bus standard advocated by U.S. Intel Corporation; specifications for this standard have been developed and published by the PCI Special Interest Group (PCI SIG), an industry association in the U.S. A PCI bus is used in particular to connect an I/O device and memory via a chipset, and is useful for speeding the transfer of data between the I/O devices and the memory.
FIG. 7 is a block diagram of a computer system using a PCI bus, and shows a computer system comprising a CPU 101, memory controller 100, memory 102, bridge circuit 103, and PCI devices 104A and 104B. The PCI devices 104A and 104B are connected to the bridge circuit 103 by the PCI bus 114, and the CPU 101, the memory 102 and the bridge circuit 103 are connected to the memory controller 100 by the processor bus 111, the memory bus 112, and the memory controller bus 113, respectively.
The PCI devices 104A and 104B can access the memory 102 via the bridge circuit 103 and the memory controller 100. The bridge circuit 103 performs connection operations to absorb differences in bus data rates, protocols and similar between the memory control bus 113 and the PCI bus 114.
Because data transfer via this bridge circuit 103 may impede the high-speed operation of the PCI bus, in order to raise throughput, a plurality of pre-fetch buffers are provided in the bridge circuit 103 (for example, Japanese Patent Laid-open No. 11-238030).
FIG. 8 is a drawing of the configuration of a computer system comprising a conventional bridge circuit 103 in which is provided a pre-fetch buffer. This computer system comprises a plurality of PCI devices 104A through 104D, a bridge circuit 103, and memory units 100 and 102. The PCI devices 104A to 104D and the memory units 100, 102 are connected by the PCI bus 114 and by the memory buses 113, 112 respectively to the bridge circuit 103.
The bridge circuit 103 has a PCI interface circuit 210, a plurality of pre-fetch buffers 221A to 221D corresponding to each of the PCI devices 104A to 104D, and a memory interface circuit 230. The PCI devices 104A to 104D each have a PCI interface circuit 240, which has a set of a REQ signal and a GNT signal.
FIG. 9 explains the sequence of operations in the computer system of FIG. 8 when a plurality of PCI devices execute memory-read requests; these operations are explained in detail below.
(1) When the PCI device 104A executes a memory read request from internal circuitry, the PCI device 104A uses a request signal REQ 331 A to send a request to the PCI bus 114.
(2) The PCI interface portion 240 of the PCI device 104A, on receiving a grant signal GNT 332 A from the bridge circuit 103, initiates a memory read request transaction according to the PCI bus protocol.
(3) The PCI interface portion 210 of the bridge circuit 103, on receiving the memory read request, assigns a pre-fetch buffer 221A corresponding to REQ 331 A/GNT 332 A, and issues a retry response to the PCI bus 114.
(4) On receiving the retry response, the PCI device 104A temporarily releases the PCI bus 114, so that another PCI device can use the PCI bus 114.
(5) The pre-fetch buffer 221A assigned as described above issues a memory read request to perform memory reading to the memory interface portion 230.
(6) The memory interface portion 230 initiates a memory read request transaction with the memory units 100 and 102.
(7) Read data is transferred from the memory units 100 and 102; and is stored in the pre-fetch buffer 221A assigned as described above.
The PCI devices 104B to 104D execute memory read requests similarly to the operations (1) through (7) above. Normally, after the memory interface portion 230 of the bridge circuit 103 executes a memory read, an extremely long time elapses before the read data is received, and so the operations (1) through (7) performed by each of the PCI devices 104A to 104D overlap with a time difference.
(8) Through operations similar to (1) through (3), the PCI device 104A executes a memory read request to the bridge circuit 103.
(9) The PCI interface portion 210 of the bridge circuit 103, on receiving the memory read request, confirms the pre-fetch buffer 221A corresponding to the REQ 331 A/GNT 332 A used by the request, and when read data is stored therein, initiates data transfer to the PCI bus 114.
Through operations similar to (8) and (9), the PCI devices 104B to 104D also execute memory read requests to the bridge circuit 103 and initiate read data transfer.
As described above, by using pre-fetch buffers, the PCI bus can be used effectively and the overall system throughput is improved.
Thus in the technology of the prior art, by preparing a plurality of pre-fetch buffers in the bridge circuit, high-speed memory access is possible through time-division of the PCI bus among a plurality of PCI devices. However, depending on the circuit configuration, there may be cases in which the number of PCI devices connected to the PCI bus may be smaller than the number of pre-fetch buffers.
For example, as shown in FIG. 10, there is the case of a computer system comprising a single PCI device 104A, a bridge circuit 103, and memory units 100 and 102. Here, the PCI device 104A and the memory units 100 and 102 are connected to the bridge circuit 103 via a PCI bus 114 and memory buses 113 and 112, respectively. The bridge circuit 103 has a plurality of pre-fetch buffers 221A to 221D. Further, the PCI device 104A has one set of REQ/GNT signals.
FIG. 11 explains the sequence of operations in the computer system of FIG. 10 when the PCI device 104A executes a memory read request; operations are indicated in detail below.
(1) When the PCI device 104A executes a memory read request, the PCI device 104A uses REQ 531 to send a request to the PCI bus 114.
(2) The PCI interface portion 240 of the PCI device 104A, on receiving a GNT 532 signal from the bridge circuit 103, initiates a memory read request transaction according to the PCI bus protocol.
(3) The PCI interface portion 210 of the bridge circuit 103, on receiving the-memory read request, assigns a pre-fetch buffer 221A corresponding to REQ 531/GNT 532, and issues a retry response to the PCI bus 114.
(4) On receiving the retry response, the PCI device 104A temporarily releases the PCI bus 114.
(5) The pre-fetch buffer 221A assigned as described above issues a memory read request to perform memory reading to the memory interface portion 230.
(6) The memory interface portion 230 initiates a memory read request transaction with the memory units 100 and 102.
(7) The PCI device 104A again executes a memory read request to the bridge circuit 103, similarly to the actions (1) to (3).
(8) The PCI interface portion 210 of the bridge circuit 103, on receiving a memory read request, confirms the pre-fetch buffer 221A corresponding to the REQ 531/GNT532 used by the request, and because read data is not yet stored therein, sends a retry response to the PCI bus 114.
(9) When the PCI device 104A, on receiving the retry response, temporarily releases the PCI bus 114. The operations (7) through (9) are repeated several times.
(10) Read data is transferred from the memory units 100 and 102, and is stored in the pre-fetch buffer 221A assigned as described above.
(11) The PCI device 104A executes a memory read request to the bridge circuit 103, similarly to the operations (1) to (3).
(12) On receiving the memory read request, the PCI interface portion 210 of the bridge circuit 103 confirms the pre-fetch buffer 221A corresponding to the REQ 531/GNT532 used by the request, and when read data is stored therein, initiates data transfer to the PCI bus 114.
In this way, when only one PCI device is connected, only one pre-fetch buffer is used corresponding to REQ/GNT, and so the PCI device can only execute one memory read request at a time.
Consequently the time from when the PCI device sends a memory read request and the bridge circuit returns a retry response until read data is stored in the pre-fetch buffer is a time of merely repeating read requests prompted by retry responses, and is completely wasted, so that overall system throughput is lowered.
Moreover, normally the time from execution of a memory read by the memory interface portion of the PCI bus until data is received is extremely long, so that even if a memory read request is again executed immediately after a retry response, the bridge circuit merely sends a retry response to the PCI bus once again, and the PCI bus is used wastefully, so that overall system throughput is lowered.
Further, when a PCI device is prompted for a memory read request through a retry response from the bridge circuit simultaneously with an initial memory read request, and the memory read request for the retry response obtains PCI bus use privileges and a memory read request transaction is initiated, because there is a large possibility that read data is not stored in the pre-fetch buffer of the bridge circuit as explained above, the PCI bus is used wastefully, and there is a high probability that overall system throughput will be lowered.